IC (integrated circuit) device fabrication on semiconductor wafers, which is presented herein only by way of example to processing and the manufacture of logic products and memory devices such as DRAMs, SRAMs, and embedded memories that contain electrically conductive links, typically employs photoresist layering and patterning to identify areas of the IC device for subsequent processing such as doping or removal. Photoresist materials are etch resistant and protect covered areas of the IC device from at least one subsequent processing step.
Photolithography is a typical wafer patterning process that employs photoresist materials sensitive to certain wavelengths of light that traditionally match the emission wavelengths of the lines of a mercury lamp such as G (436 nm), H (408 nm), or I (365 nm) or the emission wavelengths of excimer lasers such as ArF (193 nm) and KrF (248 nm). Conventional photoresist materials generally comprise positive photoresists that become soluble where exposed to light and negative photoresists that become polymerized (insoluble) where exposed to light.
In photolithography, a required pattern is first formed in expensive reticles or photomasks and then transferred into a resist layer of a wafer. Lamp sources and, more recently, certain types of laser systems have been employed for simultaneously exposing the resist layer of every IC device on a wafer to a reverse image of the photomask. Photolithography is, therefore, especially suited for batch fabrication of repeatable features on IC devices. Photolithography and other VLSI (very large scale integration) memory fabrication processes are described in detail in Handbook of Microlithography, Micromachining, and Microfabrication: Volume 1: Microlithography, Edited by P. Rai-Choudbury, SPIE Volume PM39 and VLSI Fabrication Principles: Silicon and Gallium Arsenide, by Sorab K. Ghandi, 1994, .COPYRGT. John Wiley & Sons, Inc.
The yield of an IC memory fabrication process is affected by a variety of factors. Some defects result from alignment variations of subsurface layers or patterns, and other defects result from particulate contaminants and defects in the silicon substrate. FIGS. 1, 2A, and 2B show repetitive electronic circuits 10 of an IC device 12 (FIG. 6) that are commonly fabricated to include multiple iterations of redundant circuit elements 14, such as spare rows 16 and columns 18 of memory cells 20. With reference to FIGS. 2A and 2B, circuits 10 are also designed to include particular circuit links 22 that can be removed to disconnect a defective memory cell 20, for example, and substitute a replacement redundant cell 24. Links 22 are designed with conventional link widths 25 (about 2.5 .mu.m), link lengths 26, and element-to-element pitches (center-to-center spacings) 28 of about 8 .mu.m from adjacent circuit structures or elements 30, such as link structures 38. Circuits 10, circuit elements 14, or cells 20 are tested for defects, the locations of which may be mapped into a database or program. Because the defects are unique from wafer 32 (FIG. 6) to wafer 32 and IC device 12 to IC device 12, the repair process cannot be accomplished with conventional photolithographic processes that employ fixed patterned photomasks.
However, certain lasers can precisely deliver laser pulses 34 having a laser spot 36 that is big enough to envelop and "blow" link 22 but generally small enough to avoid adjacent circuit elements 30. The early physics and computer modeling for laser-based link blowing are described by L. M. Scarfone and J. D. Chlipala, "Computer Simulation of Target Link Explosion in Programmable Redundancy for Silicon Memory," Journal of Materials Research, Vol. 1, No. 2, March-April 1986, at 368-81, and J. D. Chlipala, L. M. Scarfone, and Chih-Yuan Lu, "Computer-Simulated Explosion of Poly-Silicide Links in Laser-Programmable Redundancy for VLSI Memory Repair," IEEE Transactions on Electron Devices, Vol. 36, No. 6, June 1989, at 1056-61. Laser link blowing is now well-refined and is the method of choice for disconnecting links. The most prevalent link materials are polysilicon and like compositions, which respond well to conventional 1.047 .mu.m or 1.064 .mu.m laser wavelengths. FIG. 2C shows a conventional link structure 38 of FIG. 2A after a passivation layer 40 and link 22 have been removed by conventional laser pulse(s) 34 of prior art energy distribution.
The technology trend is, however, toward developing more complex, higher density circuits 10 or memories having more layers and smaller link structures 38 and memory cell dimensions. As polysilicon links 22 become smaller and more deeply buried, they become more difficult to sever at the conventional laser outputs and spot size limitations of 1.047 .mu.m or 1.064 .mu.m radiation. Expensive and time-consuming processes are often required to delicately etch away passivation layers 40 or other surface layers to make links 22 accessible for subsequent laser severing.
Another impediment to higher density circuits 10 or embedded memories is that the electrical resistance of the conventional polysilicon-like link materials, including polycide and disilicide, increases as dimensions shrink and thereby restricts the operating speed of memory cells 20. To address signal propagation delay associated with the higher electrical resistance attributed to polysilicon-like links 22, memory manufacturers have adopted a variety of more conductive metallic link structure materials such as aluminum, titanium, nickel, copper, tungsten, platinum, metal alloys, metal nitrides, or other metal-like materials.
Another motivation for using metallic links 22 for redundancy repairing is that these metallic links 22 are often located closer to the top of the multi-layer structure of the memory device, thus links 22 are easier for the laser beam to access without the need of etching out windows within multiple covering layers. However, many of these materials are more difficult to process using the 1.047 .mu.m or 1.064 .mu.m wavelengths of conventional link processing laser systems because these materials have higher optical reflectivities or higher melting or vaporization points than polysilicon. Generally, laser severing of these metals creates slag and debris that surround the crater and cause a lower open resistance across the severed links 22 and perhaps a circuit failure.
Higher power laser output is required to process the metallic link materials and to eliminate potential debris. However, increasing the laser output power level has deleterious effects on silicon, gallium arsenide, and other semiconductor substrates 44, other layers 42, and adjacent circuit structures 30.
Alternatively, in U.S. Pat. No. 5,265,114, Sun et al. employ wavelengths, such as 1.3 .mu.m, that exploit the absorption contrast between a target such as a metal link, and a substrate 44, such as silicon. Among other advantages, the method allows the use of higher energy laser pulses to sever links 22 without affecting the silicon substrate 44 and thus creates a greater laser energy processing window than that allowed by conventional 1.047 .mu.m and 1.064 .mu.m laser wavelengths. The open resistance across links 22 processed by this method is much higher than the resistance across links 22 severed by the conventional beams.
As links 22 and pitches 28 become smaller, spot size limitations become more critical. The selection of optical elements and their clearance from substrate 44 influence the practical spot-size limits of link-blowing laser pulses 34. For example, optical elements are generally maintained at least 10 mm above a link structure 38 to avoid contact with slag or other debris that may result from link-blowing. The conventional spot size limit for a link-blowing laser output pulse can be conveniently approximated as twice the wavelength (2.lambda.). Thus, for 1.32, 1.06, and 1.04 .mu.m-emission materials, the practical spot size limits for material removal are roughly 2.64 .mu.m, 2.12 .mu.m, and 2.08 .mu.m, respectively.
Skilled persons will appreciate that shorter wavelengths, such as 0.532 .mu.m, 0.355 .mu.m, or 0.266 .mu.m, could be employed to reduce the smallest focused laser beam spot size for material removal. However, skilled persons will also appreciate that silicon substrates 44 will strongly absorb wavelengths shorter than about 1 .mu.m such that these wavelengths will inevitably damage substrates 44, especially at the high power needed for link blowing.
The smallest focused laser spot 36 currently used in the industry for repairing 64 megabit DRAMs is about a 2.0 .mu.m diameter 46 of laser spot 36. This spot size is expected to be useful through 256 megabit and some 1 gigabit DRAM designs. FIG. 3 is a graph of spot size versus year demonstrating industry demands for smaller spot sizes as link pitch 28 and link width 25 decrease. The graph is based on a simple formula for approximating spot size demands: spot size=2 (minimum link pitch)-(system accuracy)-0.5 (link width). The graph assumes 0.5 .mu.m accuracy through the year 1997, 0.35 .mu.m accuracy through the year 1999, and 0.25 .mu.m accuracy thereafter. Accordingly, industry experts predict that spot sizes under 2 .mu.m will soon be desirable for processing links 22.